In recent years, development of display devices such as a liquid crystal display device, an EL display device, and an FED (Field Emission Display) display device has been actively carried out. The liquid crystal display device and the EL display device, in particular, have come to receive attention as a display device for a cellular phone, a portable personal computer, etc., because they are light in weight and consume small electric power. However, as more and more functions are mounted on these portable devices, highly demanded is a display device which is lighter in weight and which consumes smaller electric power.
Japanese Unexamined Patent Publication No. 8-194205/1996 (Tokukaihei 8-194205, published on Jul. 30, 1996) discloses a technique which is conventionally used for realizing a display device which consumes smaller electric power. With this, by providing a memory function to each pixel so as to switch a reference voltage corresponding to a content stored in the memory, cyclical rewriting is suspended while an identical pixel is displayed, thereby reducing electric power consumed by a drive circuit.
More specifically, as shown in FIG. 14, pixel electrodes 202 are arranged in a matrix on a first glass substrate. Between the pixel electrodes 202, scanning lines 203 and signal lines 204 are provided so as to cross at right angle. Reference lines 205 are provided in parallel to the scanning lines 203. A memory element 206 (described later) is provided at each intersection of the scanning lines 203 and the signal lines 204 in such a manner that a switch element 207 is respectively provided between the memory element 206 and the corresponding pixel electrode 202.
The scanning lines 203 are selectively controlled by a scanning line driver 208 per vertical cycle, the signal lines 204 are collectively controlled by a signal line driver 209 per horizontal cycle, and the reference lines 205 are collectively controlled by a reference line driver 210. A second glass substrate is arranged so as to face the first glass substrate at a predetermined distance, and a counter electrode is formed on a counter surface on the second glass substrate. As a display material, liquid crystal which is an electro-optic element is sealed between the two glass substrates which have surfaces formed with alignment films.
FIG. 15 is a circuit diagram showing a detailed arrangement of each pixel section in FIG. 14. Each intersection of the scanning lines 203 and the signal lines 204, which are formed so as to cross at right angles with each other, is provided with the memory element 206 for holding binary data. The memory element 206 is provided with an output section for outputting the holding information. The output section is connected to the switch element 207 having three terminals. The information held in the memory element 206 is outputted via the switch element 207. In the switch element 207, a control input terminal is supplied with the output sent from the memory element 206, one terminal is supplied with a reference voltage Vref of the reference lines 205, and the other terminal is supplied with a common voltage Vcom of the counter electrode 216, which is sent from the pixel electrode 1 via a liquid crystal layer 215. Thus, a resistance value of the switch element 207 from one terminal to the other terminal is controlled in response to the memory element 206 so as to adjust a bias state of the liquid crystal layer 215.
In the arrangement shown in FIG. 15, a positive feedback memory circuit, namely a static type memory element, is employed, using two stages of invertors 212 and 213 composed of Poly-Si (polysilicon) TFTs. Here, when a scanning voltage Vg of the scanning line 203 turns to High so as to select the scanning line 203, a TFT 211 is switched ON. At this point, a signal voltage Vsig sent from the signal line 204 is supplied to a gate terminal of the inverter 212 via the TFT 211. The output of the inverter 212 is inverted by the inverter 213 and is supplied again to the gate terminal of the inverter 212. Thus, the data written into the inverter 212 while the TFT 211 is ON are fed back to the inverter 212 in the same polarity so as to be held until the TFT 211 is switched ON again. As explained above, the publication discloses an arrangement in which one static type memory element is provided for each pixel of the liquid crystal display device.
Another arrangement for providing a static type memory element made of the polysilicon TFTs to each pixel is disclosed in U.S. Pat. No. 4,996,523 (corresponding to Japanese Unexamined Patent Publication No. 2-148687/1990 (Tokukaihei 2-148687, published on Jun. 7, 1990)). This discloses an arrangement in which a plurality of the static type memory elements are provided for each pixel composed of organic EL. FIG. 16 is a circuit diagram showing an arrangement of each pixel section in the conventional technique. In the conventional technique, each pixel is composed of (a) a plurality of memory cells m1, m2, . . . , and mn (n=4 in FIG. 16), (b) a constant electric current circuit 225, (c) transistors q1 through qn respectively controlled by data sent from each of the memory cells m1 through mn, so as to generate a reference electric current of the constant electric current circuit 225, and (d) an organic EL element 226 driven by the electric current sent from the constant electric current circuit 225. The memory cells m1 through mn corresponding to the same pixel are commonly supplied with a low electrode control signal v1, and respectively supplied with n-bit column electrode control signals b1 through bn.
The constant electric current circuit 225 is a current mirror circuit using TFTs 223 and 224. For this reason, the electric current flowing through the organic EL element 226 is determined by the reference electric current, namely a sum of all electric current flowing through the transistors q1 through qn which are connected in parallel with each other. The electric current flowing through the transistors q1 through qn is set by gate voltages of the transistors q1 through qn determined by the data stored in the memory cells m1 through mn.
As shown in FIG. 17, for example, each of the memory cells m1 through mn is so arranged to be provided with (a) a CMOS inverter 228 for inverting the input of the low electrode control signal v1, (b) a holding CMOS inverter 230, (c) a feedback CMOS inverter 231, and (d) MOS transmission gates 227 and 229 for controlling which one of the column electrode control signals b1 through bn and the output of the feedback inverter 231 is supplied to a gate of the holding inverter 230 in response to the low electrode control signal v1 and the inverting CMOS inverter 228. Thus, while the low electrode control signal v1 is selected, the MOS transmission gate 227 is turned ON and the MOS transmission gate 229 is turned OFF, so that a column input signal Bn is supplied to the gate of the CMOS inverter 230 via the MOS transmission gate 227. On the other hand, while the low electrode control signal v1 is not selected, the MOS transmission gate 227 is turned OFF and the MOS transmission gate 229 is turned ON, so that the output of the CMOS inverter 231 is fed back to the CMOS inverter 230 via the MOS transmission gate 229. Thus, the memory cells m1 through mn respectively have an arrangement of a static type memory element in which the output of the CMOS inverter 230 is fed back to the gate of the CMOS inverter 230 via the CMOS inverter 231 and the MOS transmission gate 229.
As described above, U.S. Pat. No. 4,996,523 discloses the arrangement in which the plurality of static type memory elements are provided for each pixel of the organic EL display device. Note that, in a display device using the polysilicon substrate, a driver circuit for driving the electro-optic element also can be formed with the polysilicon TFTs.
However, in the conventional technique described in Tokukaihei 8-194205, one pixel is composed of the liquid crystal layer 215, the switch element 207 for driving the liquid crystal, and the 1-bit memory element 206, as shown in FIG. 15. This causes a problem that one liquid crystal element can display only a binary monochrome image using the memory element 206, but cannot display an image having more than two tone gradations. Another problem is that these memory elements 206 can display still images, but cannot display moving images. As a result, in the conventional technique disclosed in Tokukaihei 8-194205, a scale of the driver circuit arranged around a display screen for displaying multiple tone gradations and moving images is the same as that in a display device in which the memory elements are not provided in the pixels. Namely, the scale of the driver circuit cannot be made smaller.
In this respect, when tone gradations are displayed using the plurality of static type memory elements m1 through mn arranged in each pixel as in the conventional technique disclosed in U.S. Pat. No. 4,996,523, the plurality of memory elements carry out D/A conversion when multiple tone gradations or moving images are displayed, thereby eliminating a need of the D/A converting circuit in a driver circuit. This allows the scale of the driver circuit arranged around the display screen to be made smaller.
However, as shown in FIG. 17, each of the memory elements m1 through mn uses ten TFTs, thereby causing a problem that too many TFTs are required for displaying the tone gradations. Here, it is assumed that each of the memory elements m1 through mn is composed of a total of six TFTs including two inverters and two selecting TFTs. In this case, the number of the TFTs per pixel required for displaying 4-bit tone gradations is calculated as follows; the number of TFTs required per memory cell multiplies the bit number, namely the number of the TFTs required per memory cell (6)×the bit number (4 bits)=24. Further, additional TFTs are required for displaying the tone gradations, as shown in FIG. 16.
Here, in a display device having definition of approximately 100 DPI (dot/inch), for example, the pixel size is a 250 μm square. Since three RGB colors of dots are required to be arranged in the pixel size, it is quite difficult to provide the above-calculated number of TFTs per one dot in a polysilicon process of a present design rule (4 to 2 [μm] rule).
On the other hand, in an arrangement of a dynamic type memory element in which a condenser is used as the memory element, the memory element can be arranged with a smaller number of TFTs, requiring approximately one or two TFTs per 1 bit of the memory element. However, a problem is that the dynamic type memory element cannot store and display still images, because electric charges stored in the condenser are lost through leakage electric current.